1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the invention relates to a semiconductor memory device affording a burst mode in which a plurality of data are read or written continuously in response to a single external address signal.
2. Description of the Background Art
In general, memories fall into two broad categories: random access memories (RAMs) and read only memories (ROMs). The RAMs are further divided into dynamic RAMs (DRAMs) and static RAMs (SRAMs). The DRAM stores data on the basis of the presence or absence of charges in each of the capacitors constituting the memory. The SRAM retains data in the flip-flop circuits making up the memory.
Below is a brief description of the DRAMs. The most popular of the DRAMs from the four-kilobit generation onward comprises memory cells each composed of one n-channel MOS transistor and one capacitor. Such memory cells are also adopted in today's one-megabit, four-megabit and 16-megabit DRAMs.
FIG. 22 is a circuit diagram of a memory cell in a DRAM. FIG. 23A is a plan view of a trench type memory cell structure in a DRAM, and FIG. 23B is a cross-sectional view taken on line B--B in FIG. 23A. FIGS. 22, 23A and 23B are shown on pages 158 and 160 in "Designing CMOS VLSIs" published by Baifukan in Japan, the first edition issued on Apr. 25, 1989.
As shown in FIGS. 22, 23A and 23B, a dynamic memory cell DMC for the DRAM comprises one access transistor T1 and one cell capacitor Cs. In a write operation, the potential of a word line WL is brought to the high level (i.e., logical High) to let the access transistor T1 conduct. This allows the potential of a bit line BL to be transmitted to one of two electrodes of the cell capacitor Cs, i.e., to a memory node M1, through the access transistor T1. When the potential of the bit line BL is High, the potential of the memory node M1 is also High; when the potential of the bit line BL is at the low level (i.e., logical Low), the potential of the memory node M1 is also Low. Driving the word line WL Low prevents the access transistor T1 from conducting. This causes electrical charges to be accumulated in the cell capacitor Cs. The other electrode of the cell capacitor Cs is fed with a predetermined constant cell plate potential Vcp.
In a read operation, the bit line BL is first precharged to a predetermined potential level. The potential of the word line WL is then driven High. This causes the access transistor T1 to conduct, allowing the charge in the memory node M1 to be read out onto the bit line BL through the access transistor T1. This in turn causes the potential of the bit line BL to change from the predetermined constant level. The resultant potential difference is amplified by a sense amplifier, not shown.
The SRAM will now be described briefly. Each of the static memory cells for the SRAM is composed of a bistable circuit such as a flip-flop circuit. The static memory cells fall into several categories. The cell that uses an n-channel MOS transistor as its load element is called an NMOS load type cell; the cell that utilizes a p-channel MOS transistor as its load element is called a CMOS type cell; the cell employing a high resistance as its load element is called a high resistance load type cell; and the cell adopting a p-channel MOS thin film transistor as its load element is called a TFT type cell. The most prevalent today is the high resistance load type cell.
FIG. 24 is a circuit diagram of a static memory cell in an SRAM. FIG. 25 is a plan view of the static memory cell structure in FIG. 24. FIGS. 24 and 25 are found on page 164 in the publication "Designing CMOS VLSIs" cited above.
As shown in FIGS. 24 and 25, the static memory cell SMC comprises two access transistors T2 and T3, high resistances R1 and R2 with their memory nodes M2 and M3 pulled up to a supply potential Vcc, and two driver transistors T4 and T5 cross-coupled.
In a write operation, the potential of the word line WL is brought High to let the access transistors T2 and T3 conduct. This transmits the potential of a bit line BL to the memory node M2 via the access transistor T2 and gives the potential of a bit line /BL to the memory node M3 via the access transistor T3. For example, if the bit line BL is High and the bit line /BL is Low, the potential of the memory node M2 is brought High and that of the memory node M3 Low. When the potential of the word line WL is driven Low, the access transistors T2 and T3 are both prevented from conducting. Because the high resistances R1 and R2 and the driver transistors T4 and T5 constitute a bistable circuit (i.e., flip-flop circuit), the memory nodes M2 and M3 retain the potential levels they have received.
In a read operation, the potential of the word line WL is brought High to let the access transistors T2 and T3 conduct. This transmits the potentials of the memory nodes M2 and M3 to the bit lines BL and /BL, respectively. The potentials thus transmitted are amplified by a sense amplifier, not shown.
FIG. 26 is a block diagram of a typical conventional SRAM capable of operating in burst mode. Referring to FIG. 26, the SRAM comprises a memory cell array 10, a row decoder 12, a bit line precharging circuit 14, and a sense amplifier and write driver train 42. The memory cell array 10 has word lines WL1 through WLx; bit line pairs BL1, /BL1 through BLm, /BLm intersecting the word lines; and a plurality of static memory cells SMC corresponding to the points of intersection between the word lines and the bit line pairs. The row decoder 12 selects one of the word lines WL1 through WLx by decoding an n-bit internal address signal intAdd supplied thereto. The bit line precharging circuit 14 precharges all bit line pairs BL1, /BL1 through BLm, /BLm. The sense amplifier and write driver train 42 includes m of sense amplifiers and m of write drivers 421 through 42m corresponding to the bit line pairs BL1, /BL1 through BLm, /BLm.
The SRAM further comprises an address register 22, a burst counter 32, a write control register 24 and a read/write control circuit 34. The address register 22 admits an n-bit external address signal extAdd in accordance with an address strobe signal ADS supplied through an AND gate 26. The burst counter 32 stores a k-bit address signal taken out of the n-bit external address signal extAdd from the address register 22. The stored address signal is incremented in response to an advance signal ADV given via an AND gate 28. The write control register 24 stores inside a write enable signal /WE in response to a clock signal CLOCK. Given the write enable signal /WE from the write control register 24, the read/write control circuit 34 controls the bit line precharging circuit 14, and the sense amplifier and write driver train 42.
FIG. 27 is a timing chart of signals in effect when the SRAM of FIG. 26 operates in burst read mode. In accordance with an address strobe signal ADS (waveform (c) in FIG. 27), an external advice signal Ai (waveform (b)) is admitted into the address register 22. Of the bits making up the external address signal Ai, k bits are placed into the burst counter 32. The burst counter 32 increments the k-bit address signal in response to the advance signal ADV (waveform (d)). After being incremented, the k-bit address signal is sent, together with the (n-k)-bit address signal from the address register 22, as the n-bit internal address signal intAdd to the row decoder 12. That is, the internal address signal intAdd (waveform (e)) varies continuously as illustrated in FIG. 27. The row decoder 12 selects any one of four word lines in response to the four successive internal address signals intAdd.
In this example, the write enable signal /WE (waveform (f) in FIG. 27) is at the high level. This means that the data read out on all bit line pairs BL1, /BL1 through BLm, /BLm are amplified by the respective sense amplifiers 421 through 42m. Then m-bit data Dout1 through Doutm (waveform (g)) are read out parallelly via a read bus 1, as depicted in FIG. 27.
FIG. 28 is a timing chart of signals in effect when the SRAM of FIG. 26 operates in burst write mode. The external address signal Ai is entered in response to the address strobe signal ADS (waveform (c) in FIG. 28). The external address signal Ai is then incremented in reply to the advance signal ADV (waveform (d)). Thus the internal address signal intAdd (waveform (e)) varies successively as indicated in FIG. 28.
Meanwhile, in accordance with the write enable signal /WE (waveform (f) in FIG. 28), m-bit data Din1 through Dinm (waveform (g)) are written to the write driver train 42 through a write data register 3 and a write bus 2. The m-bit data Din1 through Dinm are written simultaneously to the m of static memory cells SMC connected to the single word line selected. For example, the first m-bit data Di is written to the m of static memory cells SMC connected to the word line corresponding to the internal address signal Ai.
FIG. 29 is a block diagram of another conventional SRAM capable of operating in burst mode. Referring to FIG. 29, the SRAM has its memory cell array 10 made up of bit line pairs BL1, /BL1 through BL4m, /BL4m which are four times as many as the bit line pairs in FIG. 26. The SRAM further includes a 4m-to-m multiplexer 4, a column decoder 60 and a group 5 of m of bidirectional transfer buses. Of the 4m bit line pairs BL1, /BL1 through BL4m, /BL4m, m bit line pairs are connected by the multiplexer 4 to the sense amplifier and write driver train 42 via the bidirectional transfer bus group 5. Given a two-bit address signal from the burst counter 32, the column decoder 60 controls the multiplexer 4 in the manner outlined above.
As described, each of the dynamic memory cells DMC constituting the DRAM is made of one access transistor T1 and one cell capacitor Cs. It follows that only a very small area is occupied by each dynamic memory cell DMC and that a large-capacity DRAM is easy to fabricate using such cells. However, the DRAM has its capacitors store electrical charges that diminish over time. This makes it necessary for the DRAM to undergo a refresh operation at predetermined intervals so as to recharge the capacitors Cs.
On the other hand, the static memory cells SMC constituting the SRAM are bistable circuits and need not be refreshed at predetermined intervals. However, each static memory cell is generally composed of six elements that occupy a wider area than a single dynamic memory cell. This makes it difficult to fabricate a large-capacity SRAM.
The SRAMs shown in FIGS. 26 and 29 need not be refreshed in operation but are hard to fabricate as a large-capacity memory. One way of building a large-capacity SRAM would be to replace each static memory cell SMC with a dynamic memory cell DMC. Such a memory constitution using dynamic memory cells DMC, however, requires the refresh operation which excludes the use of burst mode while being carried out. The result is a worsened level of access efficiency for the memory.